The ever increasing complexity of integrated circuits, the quest for more specialized functions, and the characteristics and performances of which must satisfy stringent specifications imposed by the user/customer make the verification of devices for testing whether they are compliant or not with specifications increasingly difficult and laborious. The need of developing testing methods and technologies for keeping the cost of the means necessary for carrying out such complex tests on each single device low, in an economical viable manner, has fostered the development of different architectural approaches for containing overall costs.
An effective approach may be integrating on the same device an appropriate logic machine for the verification of the correct functioning, commonly called by the acronym BIST.
This logic machine may be for the verification of the logic circuitry implemented in the device and/or specifically for verifying the functioning of nonvolatile memories included in the device, typically read only memories (ROM), for example one time programmable ROMs (OTP) and the so-called few time programmable ROMs (FTP).
During the realization of the BIST system, on the basis of a specific set of data stored in the ROM, indicated as the ROM code, a control signature value is calculated, upon which the logic machine (BIST) for the verification of correct functionality is based. In order to make controls as fast as possible, the bit-string of the control signature that is generated by the logic circuitry for processing the ROM code may be chosen to be all “0”.
In practice, BIST modules for the verification of the functionality of similar ROMs but having different ROM codes have a different architecture depending on the signature that they may verify.
At the beginning of the routine, that may be executed when the self test of a ROM is commanded, the related BIST machine reads the ROM code stored in the memory, processes it, and generates the corresponding signature value. Naturally, the BIST machine executes the algorithm for generating the signature value defined while implementing the BIST. As a consequence, if the elaboration of the code by the BIST logic generates the desired result, the test is passed. If the control signature stored in the BIST system does not match the signature resulting from the execution of the self-test, the BIST system itself generates an error flag (test failed).
Generally, BIST modules are Soft-IP, that is they are defined through a hardware description language, typically through a RTL (Register Transfer Level) flow. The expected signature value of each self-test of the functioning of the memory is stored in the BIST system when the self-test circuit of the memory is generated by the RTL flow.
When the device is realized and the consequent “place and route” process is carried out, such a control signature is written and tied to the particularly stored ROM code, for which it has been calculated.
These features and peculiarities of implementation of BIST modules may not be compliant with the needs of reducing fabrication costs and with the related techniques of late programming of nonvolatile memory devices (ROM, OTP or FTP), for a more favorable flexibility of organizing the fabrication of devices destined to different uses and/or customers. Indeed, according to these cost efficient embodiments of BIST modules, the same logic machine may be unusable with a different ROM code to be stored in the memory at the time of late programming the ROM according to possibly modified customer's request.
Manufacturers often establish a certain ROM code during the design and validation phase of prototypes of a new device and based on a certain signature they define the logic circuit of the BIST to be implemented in the device. If the ROM code may be changed for complying with special customer requirements, the existing BIST may no longer be self-testable because it is helpful to modify the logic circuit of the BIST, with an attendant increase of costs for accordingly modifying the fabrication process during front-end phases for making the functions of the BIST compliant with the different ROM code that is requested.
Memories programmable during back-end phases of the fabrication process of the devices are ever more generally used in complex integrated systems. The possibility of storing in the nonvolatile memory a ROM code specific for the use of the device at one of the back-end phases of the fabrication process, allows a last-minute modification of the code for best adapting it to intervened changes in the application in terms of contents and of instructions.
The importance of flexibility in these fabrication processes may be well comprehended when considering that the so-called “Systems on Chip” (SoC) are devices destined to be manufactured for different customers and for different applications. Economies dictates that the design of a device be sufficiently flexible for being proposed for applications that are very different among them.
When an on-chip ROM memory may be programmed with a different code from the original design code, the BIST module implemented on the basis of a certain ROM code, may be no longer able to verify the functionality of the memory in which a different ROM code has been stored.
This may be significant in the case of complex SoC devices, because during the design of the device it may happen that the ROM code is modified and in these cases it may be likely that the already realized respective BIST module may not be compliant with it. During the commercial life of a device, the ROM code may be adapted to new requirements, determining a similar inadequacy of the BIST module.
In all these cases the new ROM code may be helpfully verified by connecting the device to a test machine, because the self-test BIST structure integrated on the chip may no longer be useful, thus resulting in long verification times and related costs.